set_attribute library {{
/chalmers/sw/sup/cds/hcmos9gp-9.2/CORE9GPHS_SNPS_AVT_4.1.a/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS/CORE9GPHS_Nom.lib
/chalmers/sw/sup/cds/hcmos9gp-9.2/CORX9GPHS_SNPS_AVT_7.1.a/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS/CORX9GPHS_Nom.lib
}}
read_hdl -vhdl ./vhd/custom_types.vhd ./vhd/precalc.vhd ./vhd/Init.vhd ./vhd/InitCarry.vhd ./vhd/DOTs.vhd ./vhd/gDOT.vhd ./vhd/E.vhd ./vhd/SKLANSKY.vhd ./vhd/logic_unit.vhd ./vhd/shift_unit.vhd ./vhd/mux16x1.vhd ./vhd/ALU_SKL.vhd
elaborate
synthesize -to_mapped -effort low
report timing > unconstrained_timing_gates_report.txt
report gates  >> unconstrained_timing_gates_report.txt
define_clock -name main_clk -period 1250 [find / -port Clk]
synthesize -to_mapped -effort medium
report timing > constrained_800M_timing_gates_report.txt
report gates  >> constrained_800M_timing_gates_report.txt
report timing -num_path 10 > constrained_800M_10_path_timing_report.txt
write_hdl > ./vhd/ALU_SKL.v